1. Field of the Invention
The present invention relates to integrated circuits and, particularly, to an integrated circuit including an overvoltage protection circuit for an output MOS transistor.
2. Description of Related Art
A power integrated circuit (IC), which is also called a power semiconductor, is used in vehicles and home electric appliances to control a voltage and current. Miniaturization of the power IC is required.
For example, a vehicle has an actuator that converts an electrical signal into mechanical motion for fuel control or transmission control. A power IC is used to control on/off of the current flowing into the actuator.
FIG. 9 shows a normal vehicle electric system. An example is described in “CAR ELECTRONICS AND RELIABILITY ENHANCEMENT OF IN-VEHICLE ELECTRONIC PARTS AND DEVICES”, first edition, Technical Institution Institute Co. Ltd, Jul. 31, 1989, p. 31 (FIG. 2). The vehicle electric system includes a power IC 91, an actuator 92, an ignition switch 93, a battery 94, an alternator 96, a field coil 97, and a regulator 98. The alternator 96 is connected to a battery 94 via a battery terminal 95. For example, if a user turns on the ignition switch 93, the battery 94, field coil 97, and power IC 91 are connected so that the battery 94 supplies a power supply voltage to the power IC 91 and the alternator 96 starts generating electric power.
The power IC 91 is turned on or off by a microcomputer (not shown), thereby controlling the current flowing into the actuator 92. The actuator 92 uses an equivalent circuit of inductance and resistance components, and it is called an L load due to having the inductance component. The L load is an engine valve solenoid, for example.
FIG. 10 shows an example of a circuit diagram of the power IC 91. The power IC 91 uses Metal Oxide Semiconductor Field Effect Transistor (MOSFET, which is also referred to hereinafter as MOS or MOS transistor) as a current control switch in a source follower. The power IC 91 is a high side switch since an output MOS transistor is connected closer to a battery than a load is. The load is the actuator 92 in this case.
In the power IC 91, the drain of an output MOS transistor M10 receives power through a power supply (Vbb) terminal. The gate of M10 receives a voltage which is boosted by a charge pump circuit 102 through a resistor R10. The source of M10 is connected to the actuator 92 via an output (OUT) terminal. The drain of a gate discharge MOS transistor N10 is connected between the charge pump circuit 102 and the resistor R10. The gate of N10 receives a control signal S12 and the source of N10 is connected to the OUT terminal.
A control signal S11 inputted by the microcomputer turns on or off the output of the charge pump circuit 102. The control signal S12 turns on or off the gate discharge MOS transistor N10.
Generally, there are two structural types of MOS transistors: a horizontal device in which a current flows parallel to a substrate surface, and a vertical device in which a current flows perpendicular to a substrate surface. The vertical device has a higher current-carrying capacity per unit area than the horizontal device since one of main electrodes is located in the bottom surface side of the semiconductor device. Thus, the vertical device is mainly used as a high power device. In this example, the output MOS transistor M10 is a vertical MOS transistor, and the gate discharge MOS transistor N10 is a horizontal MOS transistor.
FIG. 11 is an example of a timing chart of the power IC 91. The timing chart shows the state of each signal when the output MOS transistor M10 changes from off to on and then from on to off. The transition period until the MOS transistor is completely turned off is called “turn-off”. The following explanation simply uses the word “off” “on”, and “turn-off” to refer to the off, on, and turn-off of the output MOS transistor, respectively.
To turn on the output MOS transistor M10, the control signal S11 is set to High level and the control signal S12 is set to Low level. The boosted voltage from the charge pump circuit 102 is thereby supplied to the gate of the output MOS transistor M10 through the resistor R10. This increases a gate voltage VGS between the gate and the source of the output MOS transistor M10 to turn on the output MOS transistor M10. This allows an output current IOUT to flow into the actuator 92 so that an output voltage VOUT is applied.
On the other hand, to turn off the output MOS transistor MO,i the control signal S11 is set to Low level and the control signal S12 is set to High level. The gate discharge MOS transistor N10 is thereby turned on, and the gate charge of the output MOS transistor M10 is flows into the OUT terminal through the resistor R10 and the gate discharge MOS transistor N10. This decreases the gate voltage VGS to turn off the output MOS transistor M10. The output of the output current IOUT and the output voltage VOUT thereby stops.
As shown in the waveform of the output voltage VOUT in FIG. 11, a back electromotive force (hereinafter as back EMF) Vinv, which is a negative voltage, occurs in the turn-off period. This is because energy of ½*L*I2 is accumulated in the inductance component of the L load when a current flows into the actuator 92 in the on period, and the energy is released in the off period. The back EMF Vinv is theoretically an infinite voltage, and the voltage is applied until it reaches the output withstand voltage of the output MOS transistor M10. This can cause characteristics degradation or destruction of the output MOS transistor M10.
In order to prevent the back EMF Vinv from exceeding the output withstand voltage of the output MOS transistor M10, the power IC 91 places a dynamic clamp circuit 101 between the gate and the drain of the output MOS transistor M10. The dynamic clamp circuit 101 includes a withstand voltage diode D101 and a backflow prevention diode D102. The withstand voltage diode D101 is a Zener diode.
In the turn-off period, the output voltage VOUT decreases as the gate voltage VGS decreases, and thereby the back EMF Vinv occurs. When the output voltage VOUT decreases to a breakdown withstand voltage of the withstand voltage diode D101, the back EMF Vinv is clamped by the breakdown withstand voltage, thereby preventing the voltage from reaching the output withstand voltage of the output MOS transistor M10.
In some cases, a surge voltage called a dump surge occurs in the power IC 91. The dump surge is a positive voltage which occurs in the Vdd terminal of the power IC 91 when a battery terminal 95 is detached while an alternator 96 is generating electric power.
FIG. 12 is a timing chart when the dump surge occurs. The voltage of the Vbb terminal is usually 12V, which equals to the voltage of the battery 94. Upon occurrence of dump surge, it increases to about 60V for 0.2 to 0.4 seconds. Since the voltage of the Vbb terminal exceeds the breakdown withstand voltage of the withstand voltage diode D101 when the dump surge occurs, a clamp function is activated. This results in temporal increase in the gate voltage VGS to turn on the output MOS transistor M10, thus outputting the output current IOUT and the output voltage VOUT.
In consideration of the dump surge, it is necessary that the breakdown withstand voltage of the withstand voltage diode D101 is not less than 60V, the dump surge. This is because, if the dump surge occurs when the output MOS transistor M10 is off, the clamp function of the dynamic clamp circuit 101 is activated, which causes the output MOS transistor M10 to be broken down due to heat. It is also necessary that the output withstand voltage of the output MOS transistor M10 is not less than the breakdown withstand voltage of the withstand voltage diode D101.
For example, the breakdown withstand voltage of the withstand voltage diode D101 is set to 70V, which is a dump surge of 60V plus a margin voltage of 10V. In this case, the output withstand voltage of the output MOS transistor M10 is preferably 90V, having a margin voltage of 20V for device variation.
Since the output withstand voltage of the output MOS transistor M10 and a chip area are proportional, the chip area of this power IC increases compared to the power IC which does not have the dynamic clamp circuit 101. The increase in the chip area causes higher costs and a larger mounting surface.
A low side switch having a dynamic clamp circuit is described in Japanese Unexamined Patent Publication No. 11-32429.
As described above, the present invention has recognized that conventional integrated circuits such as power IC have the problem that placing the dynamic clamp circuit increases a chip area to cause higher costs and a larger mounting surface.